The demonstration DAQ system installed at the south pole in January
2001 contains a Phase Locked Loop (PLL) integrated circuit programmed to
phase lock a 16.8 MHz output to the 10 MHz house clock delivered by a GPS
clock. The circuitry was kluged together on top of components on
one of the test boards. The one pulse per second clock tick delivered
by the GPS clock can be on any one of 25 different phases with respect
to the 10MHz to 16.8 MHz clock coincidence. Because the test board
doubles the 16.8 MHz to 33.6 MHz, which is used to drive the internal clock
counter, the number of possible phases is reduced to 25, and the absolute
time error with respect to the GPS 1 PPS clock tick can be no more than
the width of one 33.6 MHz clock tick (29.7619 ns). This timing error
is less than one third of the resolution of the AMANDA clock.
Whether a 30 ns absolute clock error is acceptable should be discussed by physics collaborators.
The modern computer industry fertalized the development of zero phase delay clock drivers based on phase locked loops. With these components, not only is it possible for all test board subsystems to be delivered identical phase, it is also possible to cause the phase of the test board inputs to match the phase of the GPS clock. Each set of test boards will share a common 16.8 MHz clock input.
The clock distribution subsystem must also deliver a phase matched 1 PPS output which the test board subsystems will use to synchronize their internal clock counters. Each set of test boards will share a common 1 PPS clock signal.
The distribution of the clock signal represents a high potential for introducing ground loops and house noise into the test board subsystems if ordinary coax cable is used for clock distribution. Several alternatives exist.
Distribution by fiberoptic cable is imune to noise. Fiber components are, however, somewhat bulky and expensive.
Distribution by twisted pair, if done carefully, avoiding DC paths, and exploiting common mode chokes, can also do the job with relatively more convenient and familiar components. Shielded twisted pair will capture any radiation from the twisted pairs.
The clock distribution system contains a programmable logic device (PLD) in which circuitry can be implemented to actively reduce the phase error of the 16.8 MHz clock edge with respect to the one pulse per second clock tick. Absolute clock accuracy of a few nanoseconds should be possible.
The design goal is to have the phase of the 16.8 MHz clock which is input to each test board match the phase of the 10 MHz clock when the 1 pps signal goes true, and furthermore, have an enable signal go true 15 to 20 ns before the GPS clock generates its 1 PPS clock tick so that testboard clocks can be synchronized within a few ns of UT. The development of this timing system will have carry-over potential for IceCube.
GTPrzhybykski Lawrence Berkeley Lab. May 16, 2001