| Replace the 30 Megasample per second, 10-bit ADC dropped from the Analog Devices list of current products with a 40 Megasample per second product with similar precision. |
| Remove some short circuits inadvertently left in the original layout |
| Add the PC-104+ connector to make accessible to the FPGA more interrupt lines in the bus interface. |
| Add board level support for interrupting power supplied to the twisted pair. |
| Relocate oscillator and PLL components to reduce noise induction into the communications circuits. |
| Install support for easy change-over from local clock to distributed clock. |
| Install input for distributed clock which will have high immunity to noise and not cause ground loops. |
| Install support circuitry for the One Pulse-Per-Second signal from the GPS clock which is used to time synchronize test boards. |
| Install limiting amplifiers where clipping and recovery time are a problem for the signals. |
| Install more robust blow-out protection for communications DAC. |
| Resolve component interference problems associated with stacking boards. |
| Relocate RJ-45 connector on the same edge as the twisted pair input and service connections. |