CPLD Glue Logic V1.0, February 1, 2003
G. Przybylski, Lawrence Berkeley National Laboratory
Clock Repeat
Clock repeat through the PLD has been deleted in order to simplify the
DOM PCB, and to improve clock quality and noise suppression.
CPU Soft Reset and Flash Memory Reset
State Machine Description:
Inputs:
nRESET :
Bidirectional (Open Collector)
Outputs:
FLASH_RESET : Output (Open
Collector)
State Machine:
Idle state: nRESET is high, When nRESET goes low, enter state_1
State_1: Pull down both FLASH_RESET and nRESET
for ( 2^21 - 2^20) clock counts of the 20 MHz clock, then release
both FLASH_RESET and nRESET ( 2^20 - 1 ) counts of the 20
MHz clock. When done, return to Idle state.
Flash Memory Read Enable and Write Enable
Input
EB_nWE
|
Input
EB_nOE
|
Output
FLASH_nWE
|
Output
FLASH_nOE
|
1
|
1
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
Illegal State
|
|
The CPLD must repeat the read and write enable signals to the
flash memory.
PLD_TP
Undefined output. Allocated for whatever test purpose (diagnostic) the
PLD programmer sees fit.
Flash Memory Write Protect
Output line Flash_nWP .shall be left in TRI-STATE high impedance
state.
Write protect policy for the flash memory is not defined. The
hardware default (pull-up resistor on the board) places the flash in a
writable mode.
PS-UP, PS-DN, PS-ENA ADC, PLD_COMM_AD_D[0:9],
and PLD_COM_DB[7:13]
These signals have been deleted from CPLD interface.
Sluggish Start-Up Mitigation
The CPLDs (Xilinx XC2C256_TQ144)
displayed start-up inconsistent with documentation. Below a
certain temperature, the CPLD became initialized well after the other
devices started.
In order to