Digital Optical Module CPLD Description and API

0.  For Glue Logic functionality, see logic requirements.

1. Functional Address Space

1.1 Register Assignments

The following set of  sixteen registers appear at the first sixteen 'memory locations' of the  CPU at Expansion Bus addresses space when chip select EB_CS2 is activated.  Since only the lowest four address bits are decoded,  the datum accessed at will in fact be the address modulo 16.

Registers are 8-bits wide, restricted by the fact that only eight data bits, EB_D[7..0], are connected to CPLD pins. 

Word or byte access bits in the expansion bus interface are ignored.
 

Address Assignment

Hex address	Function  Address	Write Register Functionality	Read Register Functionality
%x0000000	0	SCRATCHPAD2	SCRATCHPAD2
%x0000001	1	SCRATCHPAD3	SCRATCHPAD3
%x0000002	2	SCRATCHPAD4	SCRATCHPAD4
%x0000003	3	SCRATCHPAD5	SCRATCHPAD5
%x0000004	4	SPI_CHIP_SELECT/1-Wire Select
%x0000005	5	SPI_CHIP_SELECT/1-Wire Select and I2C Data Output	I2C Data Input
%x0000006	6	SPI_CONTROL (Shared with 1-Wire)	SPI_Read_Data (Shared with 1-Wire)
%x0800007	7	Unused
%x0000008	8	Unused
%x0000009	9	SYSTEM_CONTROL	SYSTEM_STATUS0
%x000000A	10	MUX_CONTROL	SYSTEM_STATUS1
%x000000B	11	UART_CONTROL	UART_STATUS
%x000000C	12	SCRATCHPAD0	SCRATCHPAD0
%x000000D	13	SCRATCHPAD1	SCRATCHPAD1
%x000000E	14	Reboot Register
%x000000F	15	Boot Control Register	Boot Status Register

If the above address space is not sufficient, then assign EB_nCS2 to additional functionality.  Any addresses will be legal.

1.2 Expansion Bus Issues

To exert addititional control related to Flash Memory, the CPLD contains special connections.

2. Register Definitions and descriptions

2.0  Registers

2.1 Register Undefined (or scratchpad)

2.2 Register Undefined (or scratchpad)

2.3 Register Undefined (or scratchpad)

2.4 %x04 Chip Select lines for SPI interface DACs and ADC

Three protocols for serial communications between the CPU and data acquisition components (ADCs,  DACs, etc.) are supported by firmware in the DOM CPLD.  The protocols are SPI, I2C, and 1-Wire.   SPI (and Microwire) are protocols that depend on four lines: Clock, MOSI (master in, slave out),  MISO (master out, slave in) and a chip select line.  Clock can be shared among many (or all) device.  All other devices sharing MISO, MOSI and CLK line ignore those lines.  Likewise, if clock does not toggle, then all I/O and chip select lines are ignored.  This makes possible a sharing scheme with 1-Wire protocol.

I2C protocol START and STOP commands require the data line to change state when the clock is high.  All other I2C commands require level changes on the data line while the clock line is low.    
I2C devices will actually use the chip-select line for data communications.  
It may be possible for an one-wire device to share the chip select line of  an I2C device, but this has not been proven
to be possible, and the design of the current DOM prototype will not extend into this unexplored terratory.

1-Wire protocol devices extract clock and data from the same line. They also place data on the line in response to clock edges when commanded to do so.   For the IceCube DOM,  1-wire communications will be allowed on all chip select lines, provided that the SPI clock is inhibited.  

1-Wire protocol will be allowed on the chip select lines when the 1-Wire_Enable bit is set.  Otherwise, SPI protocol is assumed.

I2C protocol is a shared device protocol as well, in a somewhat more restricted sense.  Some I2C devices have programmable address (hardware) inputs.  They are polled by their hardware addresses.  Some I2C devices do not support address polling.  Therefore, hardware resources must be dedicated exclusively to those devices.  The device chip select line will be used for communication.

Write Register

Bit	Target	DOM Feature(s)	NET
0	DAC_nCS0	Serial Chip Select for SPI device	DAC_nCS0
1	DAC_nCS1	Serial Chip Select for SPI device	DAC_nCS1
2	DAC_nCS2	Serial Chip Select for SPI device	DAC_nCS2
3	DAC_nCS3	Serial Chip Select	DAC_nCS3
4	DAC_nCS4	Serial Chip Select	DAC_nCS4
5	ADC_nCS0	Serial Chip Select	ADC_nCS0
6	ADC_nCS1	Serial Chip Select	ADC_nCS1
7	MUX_nCS0	Serial Chip Select	MUX_nCS0

2.5 %x05 Additional Chip Select lines for SPI interface DACs and ADCs

 Wiret Register

Bit	Target	DOM Feature(s)	NET
0	BASE_nCS0	Chip Select	BASE_nCS0
1	BASE_nCS1	Chip Select	BASE_nCS1
2	FLASHER_nCS0	Chip Select	FLASHER_nCS
3
4	TEMP_SENSOR_DATA	Serial Output line for I2C device	TEMP_SENSOR_IO
5
6
7

2.6 %x06 SPI and 1-Wire control register

A read of Bit 0 of this register may be used by software assertain the protocol enabled. 

SPI protocol assumes that Bit 0 is low, and that one and only one SPI chip select is active.  

2.7 %x07 Unused

 Write Data

Bit	Target	DOM Feature(s)
0
1
2
3
4
5
6
7

 Read Data

Bit	Target	DOM Feature(s)
0
1
2
3
4
5
6
7

2.8 %x08 Unused

2.9 %x09 External Module Control Register

 

Bit	Target	DOM Feature(s)	NET
0	HV_PS-ENABLE	Enables High Voltage Power Output.	BASE_ON/OFF
1
2	BAROMETER_ENABLE	When asserted, powers up barometer subsystem.	BAROMETER_ENA
3
4
5	PS_DOWN	Step LED Power Supply Down	PS-UP
6	PS_UP	Step LED Power Supply Up	PS-DN
7	PS_ENABLE	LED Power Supply Enable	PS-ENA

 Read Register

2.10 %x0A ATWD Input Multiplexor control

The highest input of both  ATWDs  receives  input from wide-band analog multiplexors for the purpose of routing calibration signals to the ATWD input.

Bit	Target	DOM Feature(s)	Net
0	MUX_ENABLE0	Multiplexor chip enable	MUX_ENABLE0
1	MUX_ENABLE1	Multiplexor chip enable	MUX_ENABLE1
2	SELECT_ADDR0	Low Order Binary Address Bit	SELECT_ADDR0
3	SELECT_ADDR1	High Order Binary Address Bit	SELECT_ADDR1
4	PLL_S0	CY2907 PLL program select bit 0	PLL_S0
5	PLL_S1	CY2907 PLL program select bit 1	PLL_S1
6	AUX_CTL_WRITE	Direction Control for AUX_I/O line	<internal node>
7	AUX_I/O	MOSI bit of auxiliary connector	AUX_IO

ATWD Multiplexer Channel Assignments:

SELECT_ADDR[1:0]	MUX_ENABLE[1:0]	Monitor Entity
don't care	%x00	None
%x00	%x01	Toyocom Oscillator Output (distorted sinusoid)
%x01	%x01	40 MHz square wave (attenuated and level shifted)
%x02	%x01	PMT LED current
%x03	%x01	Flasher board LED current
%x00	%x10	Local Coincidence Signal (upper)
%x01	%x10	Local Coincidence Signal (lower)
%x02	%x10	Communications ADC input signal
%x03	%x10	Front End Pulser sample

Since the MUXes consume substantial power, it is recommended that they be disabled when not explicitly in use.   Operating both muxes at the same time is not recommended, however, the parts are protected from damage by internal output resistors.

Read Data

2.11 %x0B Communications control register

 

Bit	Target	DOM Feature(s)
0
1	DSR_CONTROL	When asserted DSR is required for communications through on-board serial interface
2
3
4
5
6
7

Bit	Datum	DOM Feature(s)
0	SERIAL_POWER	Power State of RS-232 level translator
1	SERIAL_DSR	State of DSR  input from level translator
2	SERIAL_RECEIVE_DATA	Monitor of serial port receive data
3	SERIAL_TRANSMIT_DATA	Monitor of serial port transmit data
4
5
6
7

2.12 %x0C SCRATCHPAD0

2.13 %x0D SCRATCHPAD1

2.14 %x0E Reboot Control Register

 Write Register

Bit	Target	DOM Feature(s)	Net
0	SOFT_REBOOT	Causes pull-down on the nCONFIG net.	nCONFIG
1	n/a
2	n/a
3	n/a
4	n/a
5	n/a
6	n/a
7	n/a

2.15 %x0F Boot Configuration Register

Write Register 

Bit	Target	DOM Feature(s)	NET
0	ALTERNATE_FLASH_MEMORY_MAPPING	See Flash Mapping Truth Table below	Flash_nCS0 Flash_nCS1
1	BOOT_FROM_FLASH	When asserted, causes CPU to boot from Flash Memory when initiate_reboot is asserted	BOOT_FLASH
2
3
4
5
6
7

Read Register

Bit	Datum	DOM Feature(s)	NET
0	ALTERNATE_FLASH_MEMORY_MAPPING	The state of the Flash Swapping Bit	<internal node>
1	BOOT_FROM_FLASH	The state of the BOOT_FROM_FLASH bit	BOOT_FLASH
2	INIT_DONE	High when FPGA is configured	INIT_DONE
3	nCONFIG	State of nCONFIG line from Excalibur..  High is normal.	nCONFIG
4	CONFIG_DONE	High when FPGA has initialized	CONFIG_DONE
5	INIT_DONE	State of INIT_DONE Line from Excalibur.	INIT_DONE
6	nRESET		nRESET
7

Asserting nCONFIG causes the FPGA to be cleared and causes the CPU to execute a warm boot.  

Flash Memory Mapping Truth Table

Boot from Flash