CPLD Pins for the February, 2003 DOM MB
group them by function
(7) Control Signals (Excalibur status and control) (The
kitchen sink)
nPOR
nCONFIG
nRESET
nSTATUS
INIT_DONE
CONFIG_DONE
BOOT_FLASH
(22) Expansion bus
EB_nCS[3..0]
EBD[7..0]
EBA[5..0]
EB_nOE
EB_nWE
EB_CLK
CPU-CLK (20 MHz)
(6) Flash Memory (somewhat simplified) - Implementation
FLASH_nCS[1..0]
FLASH_nOE
FLASH_nWE
(17) Flasher Interface (per the recent agreement with Wisconsin) - Implementation
FL_D[7..0]
FL_AD[5..0]
FL_nWR
FL_nOE
FL_UNDEFINED
(4) Serial (RS-232) port
RXD_Local
RXD
TXD
DSR
SER_PWR
(12) FPGA-CPLD Bus (a new interface defined to use up some
spare pins)
INT_EXT_PIN_N
FPGA_PLD_nWE
FPGA_PLD_nOE
FPGA_PLD_BUSY
FPGA_PLD_D[7..0]
(16) Serial SPI/I2C/1-Wire
SC_nCS[7..0] (4 DAC, 2 ADC, 1 Temp_Sensor, 1 spare)
SC_SCLK
SC_MOSI
SC_MISO
BASE_nCS[1..0] for PMT base power supply
BASE_SCLK
BASE_MOSI
BASE_MISO
(7) Misc
MUX_EN[1..0] used for analog front end ATWD mux
MUX_SEL[1..0] used for analog front end ATWD mux
BAROMETER_ENA
Soft_Reset
BASE_ON-OFF
(8) Test Header (subject to requirements for real needs)
AUX[7..0]
Adds up to 99 of 100