Rev 4 Change list for the Digital Optical Module Main Board

November 1, 2003


The lists below include issues noticed during the shake-down of the Rev 3 DOM MB, as well as changes that have been under consideration before Rev 3 was committed to copper.    Changes motivated by tests of the Rev 3 board fall into several categories. Some changes correct performance deficiencies. Some changes correct layout problems undetected during the final review of the Rev 3 layout files and gerber files.

The division of the list into categories arises from real or imagined boundaries in the schematic to PCB process.   Component changes can be handled entirely within the kit, though the corrections must be entered back into the basic schematics for record keeping and versioning purposes. 

Layout changes involve the tweaking of the artwork.  Some layout changes might, however, prompt the addition of textual notes/annotation of the schematic.  

Circuit changes affect the connectivity of the schematic, and possibly the set of footprints the design is built from.  These changes involve the whole process... schematic, package, and layout, and can result in a significant level of effort.  The process of revising a layout contains the risk of loosing important details/features of the previous layout.  The consequences of loosing an important layout detail can be quite severe,  up to the loss of significant functionality.


Loading Changes for Rev 4 (These changes also can apply to Rev 3 loading)

  1. Change R355 from no-load to load.  Inadvertent omission.  nReset for Flash Memory.  (Schematic error)
  2. Change CR20, CR23, CR26, and CR30 from no-load to load.  Inadvertent omission. Protection Components. (Schematic error)
  3. Change R131 from 4.7KΩ to 169 Ω to improve performance of the on-board LED pulser. (evolution)
  4. Change C157 from 47pF  to 100pF  to improve performance of the on-board LED pulser.(evolution)
  5. Change C61 from 27pF  to 100pF  to improve performance of the on-board LED pulser.(evolution)
  6. Change C56 to no-load.  This reset slow-down capacitor is no longer needed, since the CPLD change.  (Schematic indicates no-load)
  7. Change R159 to no-load in fADC bias circuit. (Schematic is correct)
  8. Change R205 to no-load affecting test pulser amplitude. (Schematic correction)
  9. Change U32, the EPC2, to no-load. (Schematic correction)
  10. Change JU1 to no-load to bring the 1.8V current monitor output into the range of the ADC input.  (Schematic correction)
  11. Change JP1 to no-load.  Loading  causes confusion with the other 14 pin connector.  (Schematic correction)
  12. Change JP8 to load. It's the high voltage power supply connector. Use connector compatible with Wisconsin's cable. (Schematic is correct)
  13. Change JP2 from a naked header to a shrouded header. Top entry is OK. (Schematic indicates keyed header)
  14. Change  R28, R65, R70, and R75 to 68 ohms (to match 130 Ω LC twisted pair) (Evolution)
  15. Change  R31, and R62 to 1.47KΩ ohms (to match 130 Ω  LC twisted pair) (Evolution)
  16. Change R106 and R112  to 24.9KΩ for optimum LC threshold..(Evolution)
  17. Require insulating sleeves on the leads of the Dearborn 10µF capacitors, C88, and C89, to prevent inadvertent contact with power distribution nets. (Evolution)
  18. Make JP6, a JTAG connector, a black shrouded header. Leave JP7, also a JTAG connector, but for a different device,  a gray shrouded header as it is now.  This will help during initial set-up, and for firmware and software updates away from LLB to identify which is for which programmable part. (It seems worth doing if the cost is small) (Evolution)

Loading Changes for Rev 3 ONLY

  1. Change T1 and T2 to Mini-Circuits brand T1-2T-KK81. (Not applicable to Rev 4.  See item 9 below)
  2. Hand mount C1 on the back of the board between JP8-17 and JP8-19.  (This removes the interference problem between C1 and JP8)
  3. CUT THESE TRACES ON BOARD BEFORE LOADING PARTS.  Cut trace on top of board at (5.7, -85.1), and cut trace on top of board at (5.7,  -95.75) to defeat short of inverting input to 5V analog. These are power connections to U62-12, and U69-12.   NO-LOAD R392 and R436.   Then, (at LBNL?) install 1KΩ resistor from U62 12 to U62-13, and another 1KΩ resistor from U69-12 to U69-13.
  4. Lift U29-pin-66 on the EPC8, and connect it to ground.  (Pin 69 of U29 is the nearest grounded pin)

Circuit Changes

  1. Change the on-board LED flasher power circuit  (TBD)  The power circuit used in previous versions has exhibited instability.
  2. Add diode from Q3 Base to Q3 Emitter, cathode to emitter, to protect transistor from reverse voltage spikes. (suggest. BAS70-04)
  3. Change capacitor at U26 input to 51 ohm series resistor. Redesignate accordingly. Change R120 to open-circuit.
  4. Repair mentor schematic at U62 and U69 pin 12.  The net property NET=5Vanalog on the resistor pin needs to be removed so the node will no longer be shorted to a power supply.
  5. Consider dropping JP12, the 4x2 header on the Power Supply page. If filtering is adequate, we don't need it for further R&D.
  6. Disconnect U5-7 from ground. Add a footprint for a jumper to ground, and specify no-load for the jumper.  (Otherwise, consider  just leaveing disconnected and deleting JU1.)
  7. Change L1, L2, L9, and L11 from Miller PM54 pkg to Delevan  SPD73-105M 1mH.... or SPD73-334M 330µH inductor. Value TBD
  8. ATWD Package change from PLCC-52 to QFP-64, or some suitable package TBD...
  9. Change T1, and T2 to Vanguard MUB510D, a 2:1 (impedance ratio) transformer to match LC twisted pair.  Revision involves change of footprint. (Possibly need higher inductance windings)
  10. Change L3, L5 and L8 in the power supply filters from Miller P54 to Delevan SPD62-103M inductors. Revision involves change of footprint
  11. Change L4, L6, and L7 in the power supply from Sumeda CDRH5D18 to Delevan SPD62-472M inductors. Revision involves change of footprint.
  12. Add diode from  U19, U20, U21, U22 pin 5 to 3.3V to protect inputs of FPGA from possible over-voltage. Suggest BAS70-04 Cathode to 3.3V power, anode to pin 5.
  13. R172 should be a 1210 package, but none of the other 200 Ω resistors need to be 1210's. Changing R63, R72, R281, R282, R283, R284, R285, R298, R299, R300, R302, R303 to 0603 or 0805 will save valuable real-estate near the FPGA, and expense, since the 1210's are rather expensive.
  14. Change the Value parameter of JP8 to specify the product model number of the connector to be used in this interface.  Indicate this connector should always be loaded. Depending on the power supply solution chosen, one of two parts will be loaded.  The smaller one will have 20 pins.
  15. Change the component reference designation U18 to JP<?>, since this RS-232 connector is not an active semiconductor device.  The existing reference designation is misleading.
  16. Add 2-pin test points to Z1-6 and to Z2-6.
  17. Add 2-pin test points to U19-2 and to U20-2
  18. Revisit the bypassing of the Excalibur CPU and the SDRAM memory to make sure adequate bypassing is provided, even when at low temperature. 
  19. Connect the EPC8 PORSEL line, U29-66, to ground to eliminate a race condition which keeps the Excalibur from booting from the EPC8 at power-on. (Alternate option is a rethinking of the nCONFIG circuit to insure it stays pulled down until the CPLD is fully initialized.)
  20. Change JP8 to a 24 pin connector. Add HV_DISABLE to pin 23 and pin 24 of JP8.  Route through R84 pin 3, pin 6, to  CPLD. U38 pin 94. Larger Connector TBD
  21. Change T4 from a Mini-Circuits part to a Vanugard MUB55D. The revision involves a footprint change.  (Possibly need higher inductance windings)

Layout Changes

  1. Relocate test point TP21 to the vicinity of  U63 and U66.  The current location of TP21 could result in the injection of noise into the board, as well as obstructing routing under the Excalibur chip.
  2. Change the footprint of U29, the EPC8 configuration memory, to accommodate the length of the pins on the chip.  See the document on enhanced configuration devices, page 2-34.
  3. Change the footprint of U129, the Corning oscillator, to match pins 1, 4 and 5 to the contacts on the package.
  4. Move C1 to the back of the board. In it's present location it interferes with the footprint of JP8, the HV power supply connector.
    (For convenience, when reloading the rest of Rev 3 boars, leave C1 out of the auto-load, and hand solder it to the back of JP8, pin 19 to pin 17.)
  5. Improve layout of flasher driver circuitry, and power distribution to flasher.switch components. Pour an island of ground plane around the flasher components.  Minimize the distance between bypasses and component leads, particularly for the MPSH81.
  6. Add more webs to support the round main board in the rectangular frame. The board/frame  is too wobbly for the loading house.
  7. Contact Mentor to get new autorouter usable on our design (RM) (done 11/11/03)
  8. Edit artwork order so that physical layers match stick-up (RM)
  9. Archive copy of REV3 (RM)
  10. Modify catalog to include exact part numbers ( and date code if practical) (RM)
  11. Review and fine tune design rules (to avoid .004 clearance in fill) (RM)
  12. Verify that all stubs are removed from final artwork (RM)
  13. Inspect for digital analog mix on inner layers in analog section (RM)
  14. Change .004 traces to .007 where possible (RM)
  15. Change .015 vias to 0.025 where possible (RM)
  16. Systematic inspection and reroute manually routed areas (RM)
  17. Full inspection and optimize clock routing (RM)
  18. Remove any unused circuitry and footprints as possible (RM)
  19. Increase gap between islands/fills  and  signal/power carrying traces/vias to reasonable value wherever possible. e.g. 0.100"
  20. Provide holes on  adjacent to the 10 µF Dearborn capacitors, C88, and C89, to allow them to be ty-wrapped to the board in case we require them to pass a vibration test.
  21. Fine tune the placement of the resistor packs in the SDRAM memory subsystem so that trace lengths fall into a narrower distribution.
For IceCube, for Lawrence Berkeley National Laboratory.
Gerald Przybylski...   11/11/03