Trade Study on Clamping Amplifiers in the PMT Signal Path

Motivation:

Reports come to us that large signals injected into a Rev 2 DOM MB produce waveforms which have anomylous non-linear behavior.

Analysis:

Examination of circuit behavior in our lab confirms the anomylous behavior.  The clamping performance depends on setting a clamping level which is not immediatly transparent.   Furthermore, the clamping behavior is much "softer" than the data sheet description would lead one to believe, however, the data sheet curves suggest a weak limiting behavior.  The observed behavior could be lived with, however, the span of the ATWD would be poorly utilized if the present behavior were tolerated.

Objective:

Determine the performance, and performance limiting components.
Propose an alternate circuit topology which will recover the full span of the ATWD for linear performance.
Test the alternate topology before recommending its inclusion in the Rev 3 DOM MB PCB

Action:

Study the linear range of HFA1135, and Burr Brown equivalent amplifiers.
Study the circuit topology.to see what penalties there are for changing the order of the amplifiers preceding ATWD Channel 0.
Studies of the common mode behavior of t he HFA1135IB suggest that the Vdd and Vee of these Clamping Amplifiers should be shifted to put center of the amplifier common mode ranges more near the expected operating voltage (2.345V).

Conclusion:

The order of the amplifiers between the delay line termination and the ATWD channel 0 input should be reversed. This reduces the adverse effects of soft limiting. This solution runs the risk of saturating the amplifier that precedes the HFA1135, however, the data sheet indicates the amplifier recovers quickly from being overdriven. 
Use HFA1135IB clamping amplifiers for performance and because they are the lowest power parts of their kind.
Provide a circuit for a positive shifted Vee and Vdd for the HFA1135IB amplifiers.  Tested same.
Use a clamping amplifier to drive ATWD Channel 0, Cahnnel 1, And Channel 2 so that all channels behave similarly with regard to clamping, and bandwidth behavior.
Change the + side clamping to 1 Vbe above Pedestal.
Set lower clamping level to clamp within a few hundred mV of  0V.