Bug 7, ATWD B pedestals jitter on Rev 4.1 DOM MBs

Status:

Closed June 30, 2004

Participants:

Kael Hanson, and Mark Krasberg, of UW, observed the problem.

Symptoms:

The pedestals of ATWD records of Rev 4.1 DOM MBs jitter unacceptably.

Approach:

History. This problem was discovered and resolved before the production of Rev 4.2 boards.

Solution:

Several digital outputs from the fADC were discovered to be routed under the RampTop control circuit for ATWD B. The layout was changed to eliminate the coupling of four digital lines into the reference circuits for ATWD B. In addition, snubbing resistors were installed on digital inputs to ATWDs. In Rev 5, 3.3V to 5V buffer drivers were installed between the FPGA and the ATWD digital inputs. A little delay is added, however, by properly driving the ATWD inputs, the power consumption should be reduced somewhat. There should be no net increase in power consumption.

Summary:

This was a problem well known to Berkeley. It was assumed that Rev 4.1 boards would not be tested in a way that would uncover this problem. There was no adequate retrofit for Rev 4.1 boards.

June 30, 2004 LBNL for IceCube