Examples from the layout of the January 3, 2003 DOM MB
Image 3.3V_IO_net_at_FPGA is an example
of satisfactory routing of the Excalibur BGA and memory BGA to the
3.3V plane.
Image N2803384 shows
the 2.5V net routing to FPGA I/O pins. The trace is quite long
and narrow, and likely to deliver poor decoupling performance
Image N2807975 shows the routing
to the SDRAM controller I/O pins. The noise performance on this net
is quite poor.
Image SD_nCLK shows the routing
to the SD_DQS0 pin on the SDRAM controller. The manual recommends
that his net loop out to the SDRAM chips and back to satisfy timing requirements.
Image VddC2 shows the routing to
a PLL power pin. which makes a long loop between filter capacitors and
FPGA input pin.
Image VddC3 shows the routing to
a PLL power pin which also makes a long looping route from filter capacitors
to FPGA input pin.
Image VddC4 shows the routing to
a PLL power pin which makes a relatively direct connection.
Examples from the layout of the April 1, 2003 DOM MB
Image N2807975 is different from Version
one of the DOM MB, but has changed in an unexpected way. This net
would best be confined to a copper island encompassing the FPGA and the
SDRAM.
Image N2803384 could be combined into
the 3.3V net, or could also have a copper island or pour to improve bypassing.
Image SD_nCLK routing to SD_DQS0, according
to the data sheet, should reach out to the memory chips and back for proper
timing. The routing of this version is, however, interesting... presumably
a result of auto-routing by Specctra.
Image Vdd_C0 could benefit from trace
fatening between capacitors and the edge of the BGA.
Image Vdd_C1 could benefit from trace
fatening between capacitors and the edge of the BGA.
Image Vdd_C2 could benefit from trace
fatening between capacitors and the edge of the BGA. Strange auto-route.
Image Vdd_C3 could benefit from trace
fatening between capacitors and the edge of the BGA. Strange auto-route.
Image Vdd_C4 could benefit from trace
fatening between capacitors and the edge of the BGA.
Image COINC_UP_A is fairly well placed
and routed.
Image COINC_UP_B could benefit from
some routing attention.
Image COINC_DOWN_A can definitely
benefit from rerouting. Very strange auto-route.
Image COINC_DOWN_B appears t obe
pretty well routed.
April 22
Image SC_SCLK_net could be broken
into segments to suppress the carrying of noise.
Additional areas of interest will be added to this page as the are encountered
in review, and during performance testing.