Notes on Waveform Capture:
Back of the Envelope Calculations

The processing of an event -- Facts and assertions

The system clock is 40 MHz (25 ns period)
Event capture in the Fast ADC takes about 4 us. Write of fast ADC data to memory can overlap with capture. (1)
Event capture in the ATWD takes about 0.4 us at about 300 MSPS
(This version of the) ATWD requires a hold time of 2.0 us before digitizing to allow the amplifier and comparator to settle. Some future version may have a shorter settling time.
The amplitude of a typical SPE is about 40 counts (by design) (2)
The pedestal offset is about 25 counts (by design) (3)
Most hits are SPE, including the 30% correlated after hits, so can be digitized more quickly by reducing the span of the Wilkinson ADC span. (4)
Digitizing to 7 bits requires about 1.575 us; digitizing to 10 bits requires 12.7875 us (5)
Most SPEs can be captured faithfully by digitizing ATWD channel 0 to 7 bits span (127 counts) (6)
Signals overflowing the SPE ADC span will be digitized at the full ATWD span, or digitized in a less sensitive ATWD channel (7)
Transferring the data from the ATWD to memory requires at least 128 clock counts (3.2 us)
Multi SPE events are rare. They will have a small effect on average dead-time, though occasionally the dead time will be large
The 300 Hz to 1 KHz SPE rate is primarily due to ₄₀K disintigrations in the glass sphere; The Muon rate is 10 Hz to 20 Hz. For convenience, let's call it 500 Hz, including muon event, and noise pulses.
30 % of SPEs are accompanied by a correlated SPE within a few us. (8)

Best Case Capture Time -- a typical SPE

0.4 + 2.0 + 1.575 + 3.2 = 7.175 us... (call it 10 us to allow for other processing in firmware)

Best Case Dead Time, assuming

100 x ( 10 us / 2 ms ) = 0.5 %

Worst Case Capture Time -- Complicated, extremely high energy event (e.g. 1E18 eV ?)

3 x ( 0.4 + 2.0 + 1.575 + 3.2 + 12.7875 + 3.2 ) = 69.4875

Aside:
The AMANDA string-18 worst-case dead-time is 200 us because of some firmware inefficiencies, resource limitations, and memory bandwidth limitations.

Notes:

1. The writing of Fast ADC data to buffer memory can be done in such a way that it doesn't affect the system dead time. The data can be transferred to memory in pipe-line fashion, while it is being acquired. It may also be transferred to memory while ATWD data is being digitized.   The writing to memory of ATWD data cannot, however, overlap with the writing of   Fast ADC data to memory.
2. The amplitude depends on the PMT HV, and the gain of two cascaded amplifier stages between the delay line on the DOM main board and the ATWD.
3. The pedestal pattern (observed in early ATWD tests) has a peak-to-peak amplitude of about 50 counts. The pedestal pattern adds to the input waveform. A pedestal bias (12 counts of DC bias) must be added to the waveform to assure that no waveform clipping occurs.
4. The span of a Wilkinson common-ramp ADC can be reduced by maintaining the same ramp rate (corresponds to ADC gain), and terminating the count at a lower power of 2 than the full span. For instance, digitize to 7 bits instead of 10.
5. The ATWD digitizer counts on both leading and trailing edge. 1023 counts requires 511.5 clock cycles of the 25 ns.clock.
6. Improving (reducing) the peak-to-peak amplitude of the pedestal pattern (which depends on masks, IC processing, and ATWD testing and selection), as well as reducing the PMT HV to reduce the amplitude of an SPE below 40 counts, can force most SPEs to fit within 64 ADC counts of the ATWD.    Reducing the span to 63 counts decreases the digitizing time by a factor of 2.
7. When reading out the ATWD, the firmware can detect that the data overflows the ADC range. e.g. %x3F for a 7 bit span, or %x1FF for a 10 bit span. State machines, digital compartors, and logic in the FPGA causes digitization with a wider span, if digitizing at a small span overflows. If digitizing at full span overflows in one channel, the state machines, and logic cause digitizing in a less sensitive ATWD channel (one preceded by less amplifier gain). The multi-step digitizing proceeds through all three ATWD channels, at gains selected by a mask, until the data read out is found to be below saturation, or ten bit digitization is done to the least sensitive ATWD channel, channel 2.   Each repetition, of course, takes more time.    Furthermore, if the read-out of the ATWD catches overflow on-the-fly, the read-out time component of the operation is unpredictable. The worst case is presented above.
8. Correlated after pulses occurring within 4 us become part of the current event record, since they appear in the Fast ADC record. Correlated after pulses occurring later than the end of the Fast ADC record cause another trigger, Ping-Pong fashion, resulting in waveform capture in the other ATWD.   A true dead-time occurs in such a case because a dead-lock for memory access will occur until the preceding event processing completes.

Glossary: