Digital Optical Module CPLD Description and API

0.  For Glue Logic functionality, see logic requirements.  See also PLD-Pins.

1. Address Space Allocation

1.0  Flash Memory at EB_nCS0

1.1 Flash Memory at EB_nCS1

1.2 DOM Main Board CPLD Registers

Since only the lowest four address bits, EBA[0:3],  are decoded,  a mirror images of the data will repeat every 16 bytes throughout the defined address space corresponding to the EB_nCS2 chip select.. 

The CPLD registers are 8-bits wide, restricted by the fact that only eight data bits, EB_D[7..0], are connected to CPLD pins. 

1.3 Flasher board CPLD Registers

2. DOM CPLD Register Definitions and Descriptions

Hex address	Function  Address	Write Register Functionality	Read Register Functionality
%x0000000	0	Not assigned	Not assigned
%x0000001	1	Not assigned	Not assigned
%x0000002	2	Not assigned	Not assigned
%x0000003	3	Not assigned	Not assigned
%x0000004	4	SERIAL_CHIP_SELECT
%x0000005	5	SERIAL_CHIP_SELECT
%x0000006	6	SPI_CONTROL (Shared with 1-Wire)	SPI_Read_Data (Shared with 1-Wire)
%x0800007	7	Not assigned	Not assigned
%x0000008	8	Not assigned	Not assigned
%x0000009	9	SYSTEM_CONTROL	SYSTEM_STATUS0
%x000000A	10	MUX_CONTROL	SYSTEM_STATUS1
%x000000B	11	UART_CONTROL	UART_STATUS
%x000000C	12	SCRATCHPAD0	SCRATCHPAD0
%x000000D	13	SCRATCHPAD1	SCRATCHPAD1
%x000000D	14	Reboot Register
%x000000F	15	Boot Control Register	Boot Status Register

If the above address space is not sufficient, then assign EB_nCS2 to additional functionality.  Any addresses will be legal.

2.0 Register Undefined (or scratchpad if CPLD resources permit)

2.1 Register Undefined (or scratchpad if CPLD resources permit)

2.2 Register Undefined (or scratchpadif CPLD resources permit)

2.3 Register Undefined (or scratchpadif CPLD resources permit)

2.4 F4 Chip Select lines for SPI interface DACs and ADC

Three protocols for serial communications between the CPU and data acquisition components (ADCs,  DACs, etc.) are supported by firmware in the DOM CPLD.  The protocols are SPI, I2C, and 1-Wire.   SPI (and Microwire) are protocols that depend on four lines: Clock, MOSI (master in, slave out),  MISO (master out, slave in) and a chip select line.  Clock can be shared among many (or all) device.  All other devices sharing MISO, MOSI and CLK line ignore those lines.  Likewise, if clock does not toggle, then all I/O and chip select lines are ignored.  This makes possible a sharing scheme with 1-Wire protocol.

I2C protocol START and STOP commands require the data line to change state when the clock is high.  All other I2C commands require level changes on the data line while the clock line is low.    
I2C devices will actually use the chip-select line for data communications.  
It may be possible for an one-wire device to share the chip select line of  an I2C device, but this has not been proven
to be possible, and the design of the current DOM prototype will not extend into this unexplored terratory.

1-Wire protocol devices extract clock and data from the same line. They also place data on the line in response to clock edges when commanded to do so.   For the IceCube DOM,  1-wire communications will be allowed on all chip select lines, provided that the SPI clock is inhibited.  

1-Wire protocol will be allowed on the chip select lines when the 1-Wire_Enable bit is set.  Otherwise, SPI protocol is assumed.

I2C protocol is a shared device protocol as well, in a somewhat more restricted sense.  Some I2C devices have programmable address (hardware) inputs.  They are polled by their hardware addresses.  Some I2C devices do not support address polling.  Therefore, hardware resources must be dedicated exclusively to those devices.  The device chip select line will be used for communication.

Asserting the chip select bit causes the appropriate hardware chip select line to be pulled low in the case of SPI devices.

The software programmer is responsible for making sure that the response from one device does not clobber that of another.

Write Register

Bit	Target	DOM Feature(s)	NET
0	SC_nCS0	Serial Chip Select for ATWD0  SPI  DAC	SC_nCS0
1	SC_nCS1	Serial Chip Select for ATWD1  SPI  DAC	SC_nCS1
2	SC_nCS2	Serial Chip Select for Threshold Control  SPI  DAC	SC_nCS2
3	SC_nCS3	Serial Chip Select for Utility Control  SPI  DAC	SC_nCS3
4	SC_nCS4	Serial Chip Select	SC_nCS4
5	SC_nCS5	Serial Chip Select for Power Monitor I2C ADC Data Out	SC_nCS5
6	SC_nCS6	Serial Chip Select for Diagnostic I2C ADC Data Out	SC_nCS6
7	SC_nCS7	Serial Chip Select for I2C Temperature Sensor Data Out	SC_nCS7

2.5F5 Additional Chip Select lines for SPI interface DACs and ADCs

 Wiret Register

Bit	Target	DOM Feature(s)	NET
0	BASE_nCS0	Chip Select for PMT Base SPI or I2C or 1-Wire device (DAC or  Ident)	BASE_nCS0
1	BASE_nCS1	Chip Select for PMT Base SPI or I2C or 1-Wire device (ADC or Ident)	BASE_nCS1
2
3
4
5
6
7

2.6 F6 SPI and 1-Wire control register

A read of Bit 0 of this register may be used by software assertain the protocol enabled. 

SPI protocol assumes that Bit 0 is low, and that one and only one SPI chip select is active.  

2.7F7 Unused

 Write Data

Bit	Target	DOM Feature(s)
0
1	HV_PS-HV-Disable	Disable (Enable) HV power supply output with EMCO (C.A.E.N.) HV module
2
3
4
5
6
7

 Read Data

Bit	Target	DOM Feature(s)
0
1
2
3
4
5
6
7

2.8F8 Unused

2.9F9 External Module Control Register

 

Bit	Target	DOM Feature(s)	NET
0	HV_PS-ENABLE	Enables High Voltage 5V main Power.	BASE_ON-OFF
1	FLASHER_ENABLE	Power up the Flasher Board interface and enable the buffer interface in this CPLD	FL_ON_OFF
2	BAROMETER_ENABLE	When asserted, powers up barometer subsystem.	BAROMETER_ENA
3	SINGLE_LED_ENABLE	Enable Power Converter chip for on-board LED anode supply
4	FLASHER_UNDEFINED	Input line to the flasher board.	FL_UNDEFINED
5
6
7

 Read Register

2.10 FA ATWD Input Multiplexor control

The highest input of both  ATWDs  receives  input from wide-band analog multiplexors for the purpose of routing calibration signals to the ATWD input.

Bit	Target	DOM Feature(s)	Net
0	MUX_ENABLE0	Multiplexor chip enable	MUX_ENABLE0
1	MUX_ENABLE1	Multiplexor chip enable	MUX_ENABLE1
2	SELECT_ADDR0	Low Order Binary Address Bit	SELECT_ADDR0
3	SELECT_ADDR1	High Order Binary Address Bit	SELECT_ADDR1
4
5
6
7

ATWD Multiplexer Channel Assignments:

SELECT_ADDR[1:0]	MUX_ENABLE[1:0]	Monitor Entity
don't care	%x00	None
%x00	%x01	Toyocom Oscillator Output (distorted sinusoid)
%x01	%x01	40 MHz square wave (attenuated and level shifted)
%x02	%x01	PMT LED current
%x03	%x01	Flasher board LED current
%x00	%x10	Local Coincidence Signal (upper)
%x01	%x10	Local Coincidence Signal (lower)
%x02	%x10	Communications ADC input signal
%x03	%x10	Front End Pulser sample

Since the MUXes consume substantial power, it is recommended that they be disabled when not explicitly in use.   Operating both muxes at the same time is not recommended, however, the parts are protected from damage by internal output resistors.

2.11 Communications control register

 

Bit	Target	DOM Feature(s)
0
1	DSR_CONTROL	When asserted DSR is required for communications through on-board serial interface
2
3
4
5
6
7

Bit	Datum	DOM Feature(s)
0	SERIAL_POWER	Power State of RS-232 level translator
1	DSR_CONTROL	State of DSR  input from level translator
2	SERIAL_RECEIVE_DATA	Monitor of serial port receive data
3	SERIAL_TRANSMIT_DATA	Monitor of serial port transmit data
4	SERIAL_DSR	DSR or DSR_CONTROL
5
6
7

The DOM MB has an RS-232 level translator chip between the RJ-45 connector and the Excalibur CPU to facilitate post production testing and debugging.    When deployed, the RS-232 translation is not needed.  The power to the chip may be removed by deinstalling a push-on type jumper.  The chip can, however, be partly powered up if any of the inputs are driven high (by the Excalibur CPU) when the Vdd of the chip is lower than the Vdd of the driving source.  So, the RXD, TXD, CTS, RTS, DSR, and DTS signals are routed through the CPLD with appropriate gating by the SERIAL_POWER signal.  

When SERIAL_POWER is high, the signals pass straight through.  When SERIAL_POWER is low, the inputs to the Excalibur CPU are pulled high, and the inputs to the RS-232 level translator are placed in High-Z state.

One exception exists.  If the SDR_CONTROL bit is high, the DSR input to the Excalibur CPU is pulled low (nDSR, actually).

2.12 SCRATCHPAD0

2.13 SCRATCHPAD1

2.14 Reboot Control Register

 Write Register

Bit	Target	DOM Feature(s)	Net
0	SOFT_REBOOT	Causes pull-down on the nCONFIG net.	nCONFIG
1	n/a
2	n/a
3	n/a
4	n/a
5	n/a
6	n/a
7	n/a

2.15 Boot Configuration Register

Write Register 

Bit	Target	DOM Feature(s)	NET
0	ALTERNATE_FLASH_MEMORY_MAPPING	See Flash Mapping Truth Table below	Flash_nCS0 Flash_nCS1
1	BOOT_FROM_FLASH	When asserted, causes CPU to boot from Flash Memory when initiate_reboot is asserted	BOOT_FLASH
2
3
4
5
6
7

Read Register

Bit	Datum	DOM Feature(s)	NET
0	ALTERNATE_FLASH_MEMORY_MAPPING	The state of the Flash Swapping Bit	<internal node>
1	BOOT_FROM_FLASH	The state of the BOOT_FROM_FLASH bit	BOOT_FLASH
2	INIT_DONE	State of INIT_DONE Line from Excalibur.	INIT_DONE
3	nCONFIG	State of nCONFIG line from Excalibur..  High is normal.	nCONFIG
4	CONFIG_DONE	High when FPGA has initialized	CONFIG_DONE
5	nPOR		nPOR
6	nRESET		nRESET
7	nSTATUS		nSTATUS

Asserting nCONFIG causes the FPGA to be cleared and causes the CPU to execute a warm boot.  

Flash Memory Mapping Truth Table

Boot from Flash