DOM Main Board Rev 4
Changes
The list of changes from Rev 3 to Rev 4 is
rather long and quite detailed, however, in the sense of
convergence to a final design, the changes are quite
minimal. The Rev 3 changes were so extensive that a new run
with the autorouter was required because of the high number of changes
in connectivity in a congested part of the board. The Rev 4
changes are so few that they can probably be done only 'by hand.'
Status
Draft status report (7.9 Mb
ppt) 11 November, 2003
Draft Rev 4 - Rev 5
Changes Review Presentation 23 April, 2004
Draft Hardware
Description Review Presentation 26 April, 2004
Schematic of DOM MB Rev 4, February 4, 2003
DOM _MB, a 6.8Mb PDF
file (From the Mentor Design Archatect View-point)
Assembly Drawings, a
4MB PDF
file (collection of Mentor output files)
Change Checklist
List of Changes for post-production
review. This list applies to the initial sample of 4 boards
produced as "first articles".
Post Manufacturing Revisions to DOM MB Rev 4.1
i..e. these modifications are included on Rev 4 DOM MBs
distributed to "customers":
Revisions added soon...
Big Images from Mentor
EPS
(11+Meg)
PDF (1.5+
Meg)
Monitoring in the Rev 4 DOM MB
The monitoring page pulls together many
bits of information spread around the schematics, and hidden in some
data sheets too...
Work in progress images:
image1 On-Board LED power supply
verification, Rev 4 main board, and traveler in sleeve.
image2 The DOM Hub computer screen;
check status.
image3 The SFT screen; Test results
from ATWD Channel 3, muxed to the oscillator input.
image4 image5
Anti-Static storage of boards to be tested, and travelers.
image6 Main board solder sample, top
side.
image7 Main board solder sample,
bottom side
image8 iimage9
Burn-in frame for installation into the big refrigerator.
image10 DOM MB mounted on support card which
slips into the burn-in card frame
image11 image12
Faulty soldering of 2-pin header into PCB. Note that the throat
of the hole is not coated with solder.
Modeling
Cascaded 2 Pole Filter: Simulation of 1PE
response; Bandwidth Simulation,
for the amplifiers on the bottom of sheet 13
Artificial Cable network: Simple RC network time domain
simulation; RLC network time domain simulation
20 MHz oscillator filter (to ATWD Mux channel 0) circuit, and
simulation.
Debugging
Eliminating Cold Pedestal Jitter
Feb 5, 2004
G. Przybylski, Lawrence Berkeley National Lab, for the IceCube experiment